Junction-type field-effect transistors (abbreviated "JFETs") exhibit less 1/f noise ("flicker noise") arising from the surface level, and exhibit a smaller substrate bias effect than MOS-type FETs. Since JFETs have a higher gate input impedance than bipolar transistors, JFETs are preferred for use as amplifiers or the like in analog circuits that require low noise and high gain.
A conventional JFET is shown in FIG. 8, in which a p-type gate region 102 is situated on the surface of an n-type semiconductor substrate. On one side of the p-type gate region 102 is an n-type drain region 103 having a high concentration of impurity, and on the opposing side of the p-type gate region 102 is an n-type source region 104 having a high concentration of impurity. An n-type channel region 105, situated beneath the gate region 102, serves to connect the source region 104 to the drain region 103. A p-type back-gate region 106 is situated beneath the channel region 105, the source region 104, and the drain region 103. The back-gate region 106 is electrically connected to the gate region 102. (Electrodes, insulating films between certain layers, and the like are not shown in FIG. 8).
In conventional JFETs, the concentration profile of impurity (here n-type) in the channel region 105 is essentially constant in a region extending from the source region 104 to the drain region 103. Also, the concentration of impurity in the source region 104 and the concentration of impurity in the drain region 103 are essentially equal. In other words, in FIG. 8, an imaginary line parallel to the surface of the semiconductor substrate can be drawn connecting a point Q inside the drain region 103, a point R on the boundary between the drain region 103 and the channel region 105, a point S on the boundary between the channel region 105 and the source region 104, and a point T inside the source region 104. The concentration distribution of n-type impurity on this line can be depicted as the curve 112 shown in FIG. 10. In FIG. 10, the horizontal axis represents positions along the imaginary straight line connecting the points Q, R, S, and T, and the vertical axis represents the impurity concentration (per cubic centimeter). As indicated by the curve 112, the impurity concentration in the drain region 103 and the source region 104 is high (at level C.sub.D). The impurity concentration drops precipitously toward the channel region 105 near the boundary between the drain region 103 and the channel region 105 and near the boundary between the source region 104 and the channel region 105. The impurity concentration distribution in the channel region 105 from point R to point S is essentially uniformly low (at level C.sub.5). Infusion of impurity in the channel region 105 is usually performed from the upper surface of the n-type semiconductor substrate. As a result, the impurity concentration in the channel region 105 may vary vertically to some extent.
In conventional JFETs having a structure like that shown in FIG. 8, a gate-source voltage V.sub.gs of inverse bias is applied across the gate region 102 and the source region 104 while a prescribed drain-source voltage V.sub.ds is applied so that a carrier will flow between the drain region 103 and the source region 104. The widths of the depletion layers 111 and 108 situated between a first diffusion region consisting of the drain region 103, the channel region 105, and a second source region 104, and a second diffusion region consisting of the gate region 102 and the back gate region 106 are controlled by the gate-source voltage V.sub.gs. Thus, the current flowing between the source and the drain is controlled.
As stated above, the bias of the gate-source voltage V.sub.gs is inverted. The drain-source voltage V.sub.ds is usually sufficient to allow a carrier to flow from the source to the drain. Hence, if the source voltage is zero, then V.sub.gs &lt;0 and V.sub.ds &gt;0 in the n-type JFET. If the voltage between the gate region 102 and the drain region 103 is equal to the gate-drain voltage V.sub.gd, then the relation .vertline.V.sub.gd .vertline.&gt;.vertline.V.sub.gs .vertline. holds since V.sub.gd =V.sub.gs -V.sub.ds. These conditions cause the depletion layers 108 and 111 to become thick on the drain region 103 side.
As shown in FIG. 8, as the drain-source voltage V.sub.ds is gradually increased from zero volts, the depletion layer 108 on the back gate region 106 side and the depletion layer 111 on the gate region 102 side are brought into contact. The point at which the depletion layer 108 and the depletion layer 111 actually contact each other on the drain region 103 side is called the "pinch-off point" 109. As the drain-source voltage V.sub.ds is further increased, the pinch-off point 109 is shifted to the drain region 103 side as shown in FIG. 9.
The difference in voltage between the drain region 103 and the pinch-off point 109 is determined by the impurity-concentration profile and the thickness of the channel region 105. Consequently, even if the pinch-off point 109 is shifted as the drain-source voltage V.sub.ds is increased, the voltage difference between the drain region 103 and the pinch-off point 109 in a typical conventional JFET remains constant.
In conventional JFETs (e.g., FIG. 9), if the drain-source voltage V.sub.ds is further increased, the pinch-off point 109 is further shifted toward the drain region 103, decreasing the distance between the pinch-off point 109 and the drain region 103 and increasing the electric field strength peripherally about the drain region 103. If the electric field strength rises above a threshold, impact ionization occurs at the periphery of the drain region 103. Impact ionization generates a charge that flows into the gate region 102 with high current. The drain-source voltage V.sub.ds should be limited so as to prevent occurrence of such a phenomenon.
Modern semiconductor devices preferably satisfy strict requirements with respect to miniaturization. To meet such requirements, the gate length (i.e., the distance between the source region 104 and the drain region 103) should be small. However, shortening the gate length decreases the distance between the pinch-off point 109 and the drain region 103. This causes an increase in electric-field strength, with a corresponding undesirable increase in the probability of impact ionization. In order to suppress impact ionization, the drain-source voltage V.sub.ds should be low; however, this reduces the resistance of the semiconductor against impact ionization.